Tag: processor

  • Arm Extends Processor Architecture to Transform IT

    Arm Extends Processor Architecture to Transform IT

    Arm today extended its processor portfolio to add two offerings that increase the performance-per-socket provided by 50% and performance-per-watt provided by 20%, respectively.

    Part of the Arm Neoverse Compute Subsystems (CSS) family of processors, these third generation Neoverse IP processors include an Arm Neoverse CSS V3 design to improve performance and Arm Neoverse CSS N3 design to improve energy consumption. Arm, for example, envisions the first instances of the N3 being used in networking and data processing units (DPUs) that require thermal design power measurement of as low as 40 watts.

    Dermot O’Driscoll, vice president of product solutions for the Infrastructure Line of Business at Arm, said Arm is already working with partners to manufacture these next-generation processors that will find their way onto system-on-chip (SOC) subsystems. Arm assumes responsibility for configuring, optimizing and validating a complete compute subsystem for key use cases on behalf of its partners, he noted.

    As part of that effort, Arm is continuing to work with partners to provide early access to SoCs to enable their software development teams to construct applications using simulation and emulation tools as next-generation platforms are being developed and deployed, he added.

    That approach helps ensure that software that is optimized for these processors is available at the time when SoCs become available, noted O’Driscoll. Variations of those Arm processors now routinely show up everywhere from the network edge to cloud computing environments to provide IT teams with an alternative to x86 processors that, so far, are not able to match the price/performance of Arm processors that are also more energy efficient.

    DevOps teams are under more pressure than ever to improve application performance without increasing the overall carbon footprint of their IT environments. Achieving those goals will require everything from more energy-efficient processors to modernized software that makes optimal use of IT infrastructure resources, especially as more inference engines are deployed to run artificial intelligence (AI) models, noted O’Driscoll.

    The challenge right now is many DevOps teams lack the tools needed to track overall energy consumption within the context of their application environment, but as DevOps continues to evolve, it will only be a matter of time before energy consumption metrics become a standard element of an observability platform being relied on to optimize DevOps workflows.

    In the meantime, as IT infrastructure environments continue to evolve, IT teams should expect to be deploying applications on a wide range of Arm, X86, graphical processor units (GPUs) and other classes of processors designed to optimize specific types of workflows. At the same time, Arm is advancing the development of “chiplets” that are optimized to run specific types of workloads within a larger SoC rather than deploying different platforms to run a specific class of processors.

    It may take a while for IT teams to wrap their arms around all the different processor options that are now at their disposal, but as the number of processor architectures being used continues to expand, the need for DevOps expertise will continue to increase.

  • What the Evolution of Specialized Hardware for AI and ML Means for DevOps

    What the Evolution of Specialized Hardware for AI and ML Means for DevOps

    The widespread adoption of artificial intelligence (AI) and machine learning (ML) technologies is accelerating the evolution of computational hardware, essential for automating complex processes and enhancing accuracy in decision-making. This acceleration is crucial in advancing computer science and data processing, especially within the various segments of AI/ML data pipelines.

    This growing demand is prompting a diverse array of chip manufacturers, from established players to emerging contenders, to innovate and lead in the development of faster and more efficient processing solutions. The primary goal? To design chips that optimize data transfer, improve memory management and enhance power efficiency. These advancements are far from incremental; they are pivotal in meeting the escalating demands of sophisticated AI and ML applications.

    This evolving hardware landscape for DevOps necessitates greater unification and automation of the various applications to the specialized AI infrastructure. With chip architectures diversifying, building the application stacks focusing on portability, performance and ease of access becomes even more crucial. The ability to seamlessly embrace multiple architectures will be key to striking the right balance for the varying technical abilities of the people who want to interact with technology.

    This article explores the implications of these hardware advancements on DevOps processes within AI and ML. Additionally, we explore strategies DevOps teams may consider to ensure applications remain efficient and portable across various chip architectures.

    The Rise of Specialized Hardware

    Historically, general-purpose hardware, including GPUs and CPUs, was the staple for many workloads. However, a clear pivot to specialized hardware is underway in artificial intelligence and machine learning, where training and inferencing demands have grown exponentially. These applications often hit performance limitations inherent in traditional hardware, partly due to the modern constraints of Moore’s Law. As a result, there is an increasing need for hardware capable of handling specific AI tasks with increased efficiency and speed. For instance, in certain machine learning scenarios, using hardware that supports single-precision floating-point computations can speed up processes without the need for the accuracy provided by double-precision computations.

    Although NVIDIA remains a dominant force in the AI chip market, the competition is heating up, with various companies offering innovative alternatives. And it’s not only from the usual suspects like Intel or AMD; Google has made strides with its Tensor Processing Units (TPUs). Amazon recently announced Trainium2, a new AI chip designed specifically for training AI systems. This chip, set to compete with Microsoft’s Maia and Google’s TPUs, underscores the growing custom AI chip development trend among major tech companies. Beyond these giants, startups such as Cerebras, SambaNova Systems, Graphcore and Tenstorrent bring fresh takes on AI hardware solutions.

    Challenges for DevOps

    As specialized hardware becomes more prevalent, the DevOps community will need to manage various new challenges, including performance portability. Performance portability refers to ensuring that applications run efficiently and perform well across varying computing architectures with minimal to no modifications.

    Cognitive computing (the broader category of AI and ML) varies in complexity, depending on the algorithms, models and creators’ unique demands for hardware-specific features. While an architecture-tailored version will certainly maximize performance on respective platforms, it complicates the process of ensuring a consistent software experience across diverse hardware.

    The challenge of system design lies in optimizing the environment for maximum efficiency, especially when the precise nature of the workload is unknown to those responsible for designing and supporting the systems.

    Of course, there are also significant and related considerations with continuous integration and continuous deployment (CI/CD) pipelines. The intricacies of CI/CD pipelines are magnified when pursuing performance portability. The need to validate software performance across multiple hardware configurations introduces a more elaborate testing matrix and can extend deployment cycles, directly affecting time-to-market requirements. Suddenly, workloads are now crossing the traditional IT infrastructure and high performance/supercomputing boundaries once defined by microservice and batch processing technologies; they are now one in a CI/CD pipeline.

    As organizations adopt specialized hardware, there’s the potential for a parallel rise in specialists focusing solely on one type of hardware or application use case. While such expertise can drive innovation and optimization for a particular platform, it also creates complexity and the potential for knowledge silos and unnecessary complexities for the operations teams and clients that use those systems.

    Leveling up Performance Portability

    Performance portability and closely related concepts, such as hardware-agnostic performance and cross-platform efficiency, are increasingly important for DevOps teams. As the technological landscape shifts, the pressing question becomes: How can the industry and DevOps teams navigate this evolution seamlessly?

    Ongoing research and development will no doubt play a key role. For example, the U.S. Department of Energy (DoE) is exploring new methodologies to support its Exascale Computing Project. This includes refining existing software libraries, pioneering new programming models and developing new tools that could eventually influence wider DevOps practices. Other researchers are developing software abstraction layers, aiming to simplify the adaptation of generic code for specific hardware configurations.

    Beyond new tools and methodologies that may come from current R&D efforts, there are many existing tools and processes that lend themselves to improving performance portability, including:

    • Containerization: Containers encapsulate applications and their dependencies in a way that helps ensure they run consistently across various environments. Open source tools like SingularityCE with Open Container Initiative (OCI) compatibility can help standardize and simplify deployment across different hardware configurations, promoting performance portability for high-performance computing and traditional IT infrastructure management.
    • Benchmarking and profiling: To achieve performance portability, it’s imperative to understand how software behaves across different architectures. Benchmarking tools provide quantitative performance measures, while profiling tools offer insights into software behavior, helping developers identify bottlenecks and areas that need optimization.
    • Code Portability Libraries: In addition to libraries like OpenCL that enable software execution across diverse hardware, recent advancements in container technologies complement this capability. For example, enhancements in container device interfaces, such as those in SingularityCE, streamline the integration of hardware-specific resources. This development aids DevOps teams in optimizing software for various hardware without extensive codebase rewrites, exemplifying the tools supporting hardware diversity and software agility in all aspects of cognitive computing.

    Of course, on top of all these tools and strategies, agile methodologies will remain essential since they prioritize iterative development, continuous feedback/improvement, and adaptability—all of which are important to fast-evolving hardware and software configurations.

    Looking Ahead: Adaptability as the Key

    As we embrace the new frontiers in AI and ML, the role of DevOps teams in navigating a constantly evolving hardware landscape becomes increasingly vital. At the heart of this journey lies the formidable challenge of application portability—a challenge that calls for technical expertise and a strategic shift toward adaptability. Enter containers emerging as indispensable tools that ensure a consistent application experience and performance across diverse platforms and handle the intricacies of portability.

    Likewise, adopting agile methodologies transcends process adherence; it embodies a mindset of flexibility and responsiveness, essential in rapid technological shifts. These approaches, far from temporary fixes, are integral to a strategy that aims to unleash the potential of AI. As DevOps teams continue to navigate these challenges, their success will depend on their adaptability and willingness to explore and integrate established and emerging technologies—particularly those excelling in scalability and efficiency. This proactive exploration and integration will be the key to surviving and thriving in this dynamic technological landscape. And yet, while we have discussed this problem regarding scientific applications, the impact is also felt on the AIOps side of the house, using AI-specific hardware with AIOps practices. While our goal here was to discuss the complexities of creating and administering systems for artificial intelligence and machine learning, we have yet to approach the security conversation, particularly with confidential computing, which is a topic for another time. Happy computing.

  • Oracle and Allies Launch ARM-Based Cloud Service

    Oracle and Allies Launch ARM-Based Cloud Service

    Oracle announced today it will make available for the first time ARM-based processors on the Oracle Cloud Infrastructure (OCI) that will also be supported as targets for deploying applications using GitHub, GitLab or Jenkins platforms. The latest Oracle service is based on processors from Ampere Computing.

    The company also revealed today it has joined the Continuous Delivery Foundation (CDF), an arm of the Linux Foundation that oversees the development of open source DevOps platforms and tools such as Jenkins and Spinnaker.

    Matt Leonard, vice president of compute for OCI, said the OCI Ampere A1 Compute provides an alternative to existing support for the x86-based processors that Oracle provides. That service will be offered at a cost of one cent per core hour with virtual machine sizes ranging from one to 80 OCPUs configured with one to 64 GB of memory per core or as a bare-metal service with 160 core and 1 TB of memory. Pricing per GB of RAM per hour is $0.0015. At that price point, Leonard said Oracle is now offering the lowest price per core of any cloud service provider.

    The growing availability of ARM-based processors is starting to have an impact on cloud economics at a time when organizations are significantly increasing the number of applications being built and deployed on public clouds. Many of those organizations, to reduce overall costs, are now actively evaluating ARM-based services, noted Leonard.

    To help jumpstart application development on the platform, Oracle is providing organizations with three classes of OCI Ampere A1 Compute services. An Oracle Cloud Free Tier gives developers $300 in free credits for 30 days. The Always Free ARM option gives developers four A1 cores and 24 GB memory, while an ARM Accelerator option provides open source developers, independent software vendors (ISV) partners, customers and universities with ARM-based development projects that need additional resources beyond what the Oracle Cloud Free Tier provides with credits for a 12-month period.

    Oracle Linux, Java, MySQL, GraalVM and the Oracle Container Engine for Kubernetes (OKE) service are also all available on the OCI Ampere A1 Compute along with integrations with DevOps platforms from GitHub, GitLab and/or Jenkins. Other vendors providing support for OCI Ampere A1 Compute include SUSE, Datadog, OnSpecta, NGINX and Genymobile.

    Oracle has also made available an Oracle Linux Cloud Developer image that enables DevOps teams to install, configure and launch a development environment via an OCI console that includes OCI client tools, utilities and common programming languages such as Java, GraalVM, Python, PHP, Node.js, Go and C/C++.

    Finally, each Ampere core is single threaded by design with its own 64 KB L1 I-cache, 64 KB L1 D-cache and a huge one MB L2 D-cache to eliminate any ‘noisy neighbor’ issues that IT organizations might otherwise encounter.

    Oracle is clearly betting that ARM-based processors will present the company with an opportunity to gain share at the expense of larger infrastructure-as-a-service (IaaS) rivals such as Amazon Web Services (AWS) and Microsoft Azure. It’s not clear to what degree IT teams might employ a different cloud service just to access ARM-based processors. However, in a world where IT teams now routinely employ multiple clouds, as far as Oracle is concerned, the playing field has never been more level.

  • Xen Project Advances Hypervisor Project

    Xen Project Advances Hypervisor Project

    The Xen Project announced this week that the latest version of the open source hypervisor can now take advantage of core scheduling, an experimental technology that enables Xen to group multiple processors together to create a single virtual central processor unit (CPU).

    Lars Kurth, chairperson for the Xen Project advisory board, said this capability also represents an important first step toward developing a more secure form of hyperthreading. Since earlier this year, many IT organizations have turned off hyperthreading because of cybersecurity concerns. However, such decisions have resulted in significant performance penalties for many applications.

    In addition to adding support for core scheduling, version 4.13 of Xen Project Hypervisor adds support for live patching and late uCode loading that makes it possible to install updates at runtime without having to reboot the hypervisor.
    The latest version of Xen also adds support for additional processors, including AMD 2nd Generation EPYC, Hygon Dhyana 18h, Raspberry Pi4 and Intel AVX512-based platforms.

    Finally, version 4.13 of Xen adds support for OP-TEE, which enables all guests to concurrently run trusted Applications on TrustZone, firmware created by ARM to isolate processors on the same system, and improvements to Dom0less, which makes it possible to partition processors running in parallel.

    The Xen Project Group also announced it has created a Functional Safety Working Group, which is committed to making the Xen hypervisor compatible with ASIL-B requirements, a set of compliance requirements defined by the automotive industry. That effort represents a significant challenge because it requires code and development processes to comply with key tenets of ISO 26262, a set of standards for embedding electronics into any road vehicle.

    The Xen Group is also working on developing a secret-free hypervisor, which Kurth said will play a critical role in thwarting side-channel cybersecurity attacks. Cybercriminals can employ side-channel attacks to break encryption algorithms by measuring and analyzing the physical attributes such as the amount of radiation being generated by a processor.

    Kurth said version 4.13 represents a major milestone in the ongoing development of Xen. In the future, Xen will also be able to take advantage of the Rust-vmm project being led by Intel that will make it possible for a processor to run multiple types of hypervisors in a modular fashion.  In addition to providing a more agile way of isolating virtual machines, Rust-vmm will reduce the amount of time required to spin up a virtual machine. Specifically, Intel is trying to make it easier for a processor to be able to run different classes of hypervisors that are optimized for legacy monolithic applications and cloud-native applications based on containers that require a much lighter-weight hypervisor.

    It’s not clear to what degree advances in technologies such as core scheduling will influence the selection of hypervisors and virtual machines. However, from a DevOps perspective, it’s clear core capabilities being added to the next generation of hypervisors will not only improve application performance, but they should also significantly advance best DevSecOps practices.

    — Mike Vizard